create_clock -name sysclk -period 40 -waveform {0 20} [get_ports {sysclk}]
create_generated_clock -name MX_PLL_CLK0 -source [get_ports {sysclk}] -master_clock {sysclk} -phase 0 -multiply_by 8 [get_nets {mypll_u/clk0_out}]